Many deposition processes have difficulty filling the small trenches and other gap features used in current semiconductor processing schemes. Individual trenches and other gap type features produced in any given technology node have principal dimensions that are significantly smaller than the critical dimensions that define the current technology. Thus, it is not unusual to find gaps on the order of 100 nm or less. In future years, feature sizes will shrink to even smaller dimensions. Unless the processes are extremely conformal, the gaps pinch off at their necks. Compounding the problem is the fact that many gaps have relatively high aspect ratios, for example, at least 5:1. Examples of situations where one can find high aspect ratio dimensions and geometries include damascene copper line processes, shallow trench isolation, and interlayer dielectric (ILD) applications.
Filling such trenches in a reliable manner, while avoiding voids in the fill material is particularly challenging at this scale. Current processes including Physical Vapor Deposition (PVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD), including High Density Plasma Chemical Vapor Deposition (HDP CVD), each of which presents some issues for filling small dimension, high aspect ratio features. Conformal deposition techniques may be inappropriate for situations where the dimension of the neck is narrower than the rest of the feature. This is because the conformal nature of the deposition leads to “pinching off”, where the reentrant features are not completely filled before the entrance to the feature is sealed off. In addition, conformal deposition often leads to weak spots or seams in structures with vertical walls.
Therefore, improved deposition techniques for creating void free fill in high aspect ratio dimensioned features are needed.